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BQ4014MB-120

BQ4014MB-120 DataSheet Texas Instruments 256Kx8 Nonvolatile SRAM

256Kx8 Nonvolatile SRAM

Texas Instruments

779.853 千字節

11 頁

Maker Site:
http://www.ti.com/

Texas Instruments

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---Full Text Search Engine--- BQ4014MB-120 Texas Instruments
---Full Text Search Engine--- 256Kx8 Nonvolatile SRAM

BQ4014YMB-120 BQ4014Y BQ4014 SLUS122 BQ4014MB-120

BQ4014MB-120	[Texas Instruments] 256Kx8 Nonvolatile SRAM
BQ4014MB-120	[TI[Texas Instruments]] 256Kx8 Nonvolatile SRAM

bq4014/bq4014Y
256Kx8 Nonvolatile SRAM
Features
(R) Data retention in the absence of power (R) Automatic write-protection during power-up/power-down cycles (R) Industry-standard 32-pin 256K x 8 pinout (R) Conventional SRAM operation; unlimited write cycles (R) 10-year minimum data retention in absence of power (R) Battery internally isolated until power is applied
General Description
The CMOS bq4014 is a nonvolatile 2,097,152-bit static RAM organized as 262,144 words by 8 bits. The integral control circuitry and lithium energy source provide reliable nonvolatility coupled with the unlimited write cycles of standard SRAM. The control circuitry constantly monitors the single 5V supply for an out-of-tolerance condition. When VCC falls out of tolerance, the SRAM is unconditionally write-protected to prevent inadvertent write operation. At this time the integral energy
source is switched on to sustain the memory until after VCC returns valid. The bq4014 uses extremely low standby current CMOS SRAMs, coupled with small lithium coin cells to provide nonvolatility without long write-cycle times and the writecycle limitations associated with EEPROM. The bq4014 requires no external circuitry and is compatible with the industry-standard 2Mb SRAM pinout.
Pin Connections
Pin Names
A0-A17 DQ0-DQ7 CE OE WE NC VCC VSS Address inputs Data input/output Chip enable input Output enable input Write enable input No connect +5 volt supply input Ground
Block Diagram
Selection Guide
Part Number bq4014 -85 bq4014 -120
Sept. 1992
Maximum Access Time (ns) 85 120
Negative Supply Tolerance -5% -5%
Part Number bq4014Y -85 bq4014Y -120
Maximum Access Time (ns) 85 120
Negative Supply Tolerance -10% -10%
1
bq4014/bq4014Y Functional Description
When power is valid, the bq4014 operates as a standard CMOS SRAM. During power-down and power-up cycles, the bq4014 acts as a nonvolatile memory, automatically protecting and preserving the memory contents. Power-down/power-up control circuitry constantly monitors the VCC supply for a power-fail-detect threshold VPFD. The bq4014 monitors for VPFD = 4.62V typical for use in systems with 5% supply tolerance. The bq4014Y monitors for VPFD = 4.37V typical for use in systems with 10% supply tolerance. When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All outputs become high impedance, and all inputs are treated as "don't care." If a valid access is in process at the time of power-fail detection, the memory cycle continues to completion. If the memory cycle fails to terminate within time tWPT, write-protection takes place. As VCC falls past VPFD and approaches 3V, the control circuitry switches to the internal lithium backup supply, which provides data retention until valid VCC is applied. When VCC returns to a level above the internal backup cell voltage, the supply is switched back to VCC. After VCC ramps above the VPFD threshold, write-protection continues for a time tCER (120ms maximum) to allow for processor stabilization. Normal memory operation may resume after this time. The internal coin cells used by the bq4014 have an extremely long shelf life and provide data retention for more than 10 years in the absence of system power. As shipped from Benchmarq, the integral lithium cells are electrically isolated from the memory. (Self-discharge in this condition is approximately 0.5% per year.) Following the first application of VCC, this isolation is broken, and the lithium backup provides data retention on subsequent power-downs.
Truth Table
Mode Not selected Output disable Read Write CE H L L L WE X H H L OE X H L X I/O Operation High Z High Z DOUT DIN Power Standby Active Active Active
Absolute Maximum Ratings
Symbol VCC VT TOPR TSTG TBIAS TSOLDER Note: Parameter DC voltage applied on VCC relative to VSS DC voltage applied on any pin excluding VCC relative to VSS Operating temperature Storage temperature Temperature under bias Soldering temperature Value -0.3 to 7.0 -0.3 to 7.0 0 to +70 -40 to +70 -10 to +70 +260 Unit V V C C C C For 10 seconds VT  VCC + 0.3 Conditions
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Sept. 1992
2
bq4014/bq4014Y
Recommended DC Operating Conditions (TA = 0 to 70C)
Symbol VCC VSS VIL VIH Note: Parameter Supply voltage Supply voltage Input low voltage Input high voltage Minimum 4.5 4.75 0 -0.3 2.2 Typical 5.0 5.0 0 Maximum 5.5 5.5 0 0.8 VCC + 0.3 Unit V V V V V Notes bq4014Y bq4014
Typical values indicate operation at TA = 25C.  VCC  VCCmax) Unit A A V V mA mA Conditions/Notes VIN = VSS to VCC CE = VIH or OE = VIH or WE = VIL IOH = -1.0 mA IOL = 2.1 mA CE = VIH CE  VCC - 0.2V, 0V  VIN  0.2V, or VIN  VCC - 0.2 Min. cycle, duty = 100%, CE = VIL, II/O = 0mAV, A17 < VIL or A17 > VIH bq4014 bq4014Y
DC Electrical Characteristics (TA = 0 to 70C, VCCmin
Symbol ILI ILO VOH VOL ISB1 ISB2 Parameter Input leakage current Output leakage current Output high voltage Output low voltage Standby supply current Standby supply current Minimum 2.4 Typical 5 2.5
Maximum 2 2 0.4 12 5
ICC
Operating supply current
4.55
75 4.62 4.37 3
110 4.75 4.50 -
mA V V V
VPFD VSO Note:
Power-fail-detect voltage Supply switch-over voltage
4.30 -
Typical values indicate operation at TA = 25C, VCC = 5V.
Capacitance (TA = 25C, F = 1MHz, VCC = 5.0V)
Symbol CI/O CIN Note: Parameter Input/output capacitance Input capacitance Minimum Typical Maximum 40 40 Unit pF pF Conditions Output voltage = 0V Input voltage = 0V
These parameters are sampled and not 100% tested.
Sept. 1992
3
bq4014/bq4014Y
AC Test Conditions
Parameter Input pulse levels Input rise and fall times Input and output timing reference levels Output load (including scope and jig) Test Conditions 0V to 3.0V 5 ns 1.5 V (unless otherwise specified) See Figures 1 and 2
Figure 1. Output Load A
Figure 2. Output Load B
Read Cycle
Symbol tRC tAA tACE tOE tCLZ tOLZ tCHZ tOHZ tOH
(TA = 0 to 70C, VCCmin  VCC  VCCmax) -85 Parameter Min. 85 5 0 0 0 10 Max. 85 85 45 35 25 -120 Min. 120 5 0 0 0 10 Max. 120 120 60 45 35 Unit ns ns ns ns ns ns ns ns ns Output load A Output load A Output load A Output load B Output load B Output load B Output load B Output load A Conditions
Read cycle time Address access time Chip enable access time Output enable to output valid Chip enable to output in low Z Output enable to output in low Z Chip disable to output in high Z Output disable to output in high Z Output hold from address change
Sept. 1992
4
bq4014/bq4014Y
Read Cycle No. 1 (Address Access) 1,2
Read Cycle No. 2 (CE Access) 1,3,4
Read Cycle No. 3 (OE Access) 1,5
Notes:
1. WE is held high for a read cycle. 2. Device is continuously selected: CE = OE = VIL. 3. Address is valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Device is continuously selected: CE = VIL.
Sept. 1992
5
bq4014/bq4014Y
Write Cycle
Symbol tWC tCW tAW tAS tWP tWR1 tWR2 tDW tDH1 tDH2 tWZ tOW Notes: (TA = 0 to 70C, VCCmin  VCC  VCCmax) -85 Parameter Write cycle time Chip enable to end of write Address valid to end of write Address setup time Write pulse width Write recovery time (write cycle 1) Write recovery time (write cycle 2) Data valid to end of write Data hold time (write cycle 1) Data hold time (write cycle 2) Write enabled to output in high Z Output active from end of write Min. 85 75 75 0 65 5 15 35 0 10 0 0 Max. 30 -120 Min. 120 100 100 0 85 5 15 45 0 10 0 0 Max. Units 40 ns ns ns ns ns ns ns ns ns ns ns ns (1) (1) Measured from address valid to beginning of write. (2) Measured from beginning of write to end of write. (1) Measured from WE going high to end of write cycle. (3) Measured from CE going high to end of write cycle. (3) Measured to first low-to-high transition of either CE or WE. Measured from WE going high to end of write cycle. (4) Measured from CE going high to end of write cycle. (4) I/O pins are in output state. (5) I/O pins are in output state. (5) Conditions/Notes
1. A write ends at the earlier transition of CE going high and WE going high. 2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition of CE going low and WE going low. 3. Either tWR1 or tWR2 must be met. 4. Either tDH1 or tDH2 must be met. 5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in high-impedance state.
Sept. 1992
6
bq4014/bq4014Y
Write Cycle No. 1 (WE-Controlled) 1,2,3
Write Cycle No. 2 (CE-Controlled) 1,2,3,4,5
Notes:
1. CE or WE must be high during address transition. 2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the outputs must not be applied. 3. If OE is high, the I/O pins remain in a state of high impedance. 4. Either tWR1 or tWR2 must be met. 5. Either tDH1 or tDH2 must be met.
Sept. 1992
7
bq4014/bq4014Y
Power-Down/Power-Up Cycle (TA = 0 to 70C)
Symbol tPF tFS tPU Parameter VCC slew, 4.75 to 4.25 V VCC slew, 4.25 to VSO VCC slew, VSO to VPFD (max.) Minimum 300 10 0 Typical Maximum Unit s s s Time during which SRAM is write-protected after VCC passes VPFD on power-up. TA = 25C. (2) Delay after VCC slews down past VPFD before SRAM is write-protected. Conditions
tCER
Chip enable recovery time
40
80
120
ms
tDR
Data-retention time in absence of VCC Write-protect time
10
-
-
years s
tWPT Notes:
40
100
150
1. Typical values indicate operation at TA = 25C, VCC = 5V. 2. Batteries are disconnected from circuit until after VCC is applied for the first time. tDR is the accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode may affect data integrity.
Power-Down/Power-Up Timing
Sept. 1992
8
bq4014/bq4014Y
Data Sheet Revision History (Sept. 1992 Changes From Sept. 1990)
Clarification of ICC test conditions, page 3.
MB: 32-Pin B-Type Module
32-Pin MB (B-Type Module)
Dimension A A1 B C D E e Minimum 0.365 0.015 0.017 0.008 2.070 0.710 0.590 Maximum 0.375 0.023 0.013 2.100 0.740 0.630 0.110 0.150 0.310
G 0.090 L 0.120 S 0.275 All dimensions are in inches.
Sept. 1992
9
bq4014/bq4014Y
Ordering Information
bq4014 MB Temperature:
blank = Commercial (0 to +70C)
Speed Options:
85 = 85 ns 120 = 120 ns
Package Option:
MB = B-type module
Supply Tolerance:
no mark = 5% negative supply tolerance Y = 10% negative supply tolerance
Device:
bq4014 256K x 8 NVSRAM
Sept. 1992
10
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